Filed of the Invention
The present invention relates to a semiconductor device and its manufacturing method, and in particular, to a technology that is effective when being applied to an HCI (hot carrier injection) accelerated stress test.
Description of the Related Art
With miniaturization of the MOS transistor, temperature rise at the time of product operation due to heating caused by a current that flows between the drain and the source at the time of gate ON has become a problem. In particular, since three-dimensional structure transistors such as a FinFET have a structure where heat generated by the current can hardly escape by diffusion, the above-mentioned temperature rise increases considerably.
This temperature rise also poses a problem that reliability of the FinFET is affected. In particular, HCI (Hot Carrier Injection) degradation that is degradation when a current flows between a drain and a source at the time of the gate ON is largely affected.
However, since an AC operation is performed at the time of real circuit operation, an actual temperature rise amount is mitigated as compared with that at the time of DC operation (DC stress), and becomes a temperature rise in the extent of 2° C. to 3° C. usually, which can be ignored. However, since the accelerated stress test at the time of estimating an HCI lifetime of the MOS transistor is carried out normally under DC stress, an influence of the temperature rise due to heating is large and degradation thereof is worst case at high temperature; therefore, the HCI lifetime is likely to be much overestimated.
Therefore, for exact lifetime prediction, it is necessary to measure the temperature rise due to heating at the time of the DC stress exactly and to perform correction on the temperature at the time of AC operation by correcting the temperature rise amount from temperature dependence of the HCI lifetime.
There is a technology like Patent Document 1 as a background art of this technical field. Patent Document 1 discloses a “semiconductor integrated circuit having a function of compensating a delay characteristic in the case of a situation where worst case at low temperature occurs.
Moreover, Patent Document 2 discloses a “FinFET having multiple fin heights and its formation method.”
Moreover, Nonpatent Document 1 discloses a “technology of analyzing an influence of self-heating at the time of FinFET operation on HCI reliability.”